Embodiments of the present invention relate to integrated circuits and the processing for the manufacture of semiconductor devices. More particularly, embodiments of the invention provide a method and a device for forming a twin bit cell structure for semiconductor integrated circuit devices, but it would be recognized that the invention has a much broader range of applicability. In a specific embodiment, the present invention provides a method for manufacturing a twin-bit structure cell with a hafnium oxide layer and a nano-crystalline silicon layer that are used together for storing charges.
Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Conventional integrated circuits provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of integrated circuits.
Increasing circuit density has not only improved the complexity and performance of integrated circuits but also has provided lower cost parts to the consumer. An integrated circuit or chip fabrication facility can cost hundreds of millions, or even billions, of U.S. dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of integrated circuits on it. Therefore, by making the individual devices of an integrated circuit smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in the fabrication of integrated circuits has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout or both needs to be changed. An example of such limitation lies in the manufacturing of memory devices. As the feature size continues to shrink, a twin bit cell structure will become more difficult to design and manufacture as it is difficult to control the gates independently.
One of the challenges in the semiconductor processing has been the manufacturing of twin-bit cell structures for non-volatile memory devices, such as the widely used flash based memory devices. Among other things, the conventional system and method for manufacturing cells with twin-bit structures face limitations when further scaling down of the cell size is required.
From the above, it is seen that improved techniques and improved material designs for the manufacturing of twin bit cell structures for non-volatile memory devices are desired.